Research Article

An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Figure 6

Basic function of a VGLC.
180216.fig.006a
(a) Arith. Mode
180216.fig.006b
(b) Shift-resistor Mode
180216.fig.006c
(c) Random Logic Mode
180216.fig.006d
(d) Misc. Logic Mode
180216.fig.006e
(e) Wide-range MUX Mode