Table of Contents Author Guidelines Submit a Manuscript
International Journal of Reconfigurable Computing
Volume 2008, Article ID 180216, 14 pages
http://dx.doi.org/10.1155/2008/180216
Research Article

An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Graduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Kumamoto 860-8555, Japan

Received 1 March 2008; Revised 15 May 2008; Accepted 21 August 2008

Academic Editor: Philip Leong

Copyright © 2008 Motoki Amagasaki et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. Y. Satou, M. Amagasaki, H. Miura et al., “An embedded reconfigurable logic core based on variable grain logic cell architecture,” in Proceedings of International Conference on Field Programmable Technology (ICFPT '07), pp. 241–244, Kitakyushu, Japan, December 2007.
  2. R. Yamaguchi, M. Amagasaki, K. Matsuyama, M. Iida, and T. Sueyoshi, “A novel variable grain logic cell architecture with multifunctionality,” in Proceedings of IEEE Region 10 Annual International Technical Conference (TENCON '07), pp. 1–4, Taipei, Taiwan, October-November 2007.
  3. M. Amagasaki, R. Yamaguchi, K. Matsuyama, M. Iida, and T. Sueyoshi, “A variable grain logic cell architecture for reconfigurable logic cores,” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL '07), pp. 550–553, Amsterdam, The Netherlands, August 2007. View at Publisher · View at Google Scholar
  4. M. Amagasaki, T. Shimokawa, K. Matsuyama et al., “Evaluation of variable grain logic cell architecture for reconfigurable device,” in Proceedings of IFIP International Conference on Very Large Scale Integration (VLSI-SoC '06), vol. 2, pp. 198–203, Nice, France, October 2006. View at Publisher · View at Google Scholar
  5. K. Leijten-Nowak and J. L. van Meerbergen, “An FPGA architecture with enhanced datapath functionality,” in Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '03), pp. 195–204, Monterey, Calif, USA, February 2003.
  6. K. Leijten-Nowak and J. L. van Meerbergen, “Embedded reconfigurable logic core for DSP applications,” in Proceedings of 12th International Conference on Field-Programmable Logic and Applications (FPL '02), pp. 89–101, Montpellier, France, September 2002.
  7. S. J. E. Wilton, C. H. Ho, P. H. W. Leong, W. Luk, and B. Quinton, “A synthesizable datapath-oriented embedded FPGA fabric,” in Proceedings of the 15th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '07), pp. 33–41, Monterey, Calif, USA, February 2007. View at Publisher · View at Google Scholar
  8. H. Amano, A. Jouraku, and K. Anjo, “A dynamically adaptive hardware on dynamically reconfigurable processor,” IEICE Transactions on Communications, vol. E86-B, no. 12, pp. 3385–3391, 2003. View at Google Scholar
  9. A. Marshall, T. Stansfield, I. Kostarnov, J. Vuillemin, and B. Hutchings, “A reconfigurable arithmetic array for multimedia applications,” in Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '99), pp. 135–143, Monterey, Calif, USA, February 1999. View at Publisher · View at Google Scholar
  10. T. Sugawara, K. Ide, and T. Sato, “Dynamically reconfigurable processor implemented with IPFlex's DAPDNA technology,” IEICE Transactions on Information and Systems, vol. E87-D, no. 8, pp. 1997–2003, 2004. View at Google Scholar
  11. D. Cherepacha and D. Lewis, “DP-FPGA: an FPGA architecture optimized for datapaths,” VLSI Design, vol. 4, no. 4, pp. 329–343, 1996. View at Publisher · View at Google Scholar
  12. J. G. Delgado-Frias, M. J. Myjak, F. L. Anderson, and D. R. Blum, “A medium-grain reconfigurable cell array for DSP,” in Proceedings of the IASTED International Conference on Circuits, Signals, and Systems (CSS '03), pp. 231–236, Cancun, Mexico, May 2003.
  13. H. Parandeh-Afshar, P. Brisk, and P. Ienne, “A novel FPGA logic block for improved arithmetic performance,” in Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays (FPGA '08), pp. 171–180, Monterey, Calif, USA, February 2008. View at Publisher · View at Google Scholar
  14. Altera, Inc., Altera Stratix II Data Sheet, 2005.
  15. Altera, Inc., Altera Stratix III Data Sheet, 2007.
  16. Xilinx, Inc., Xilinx Virtex-5 Data Sheet, 2007.
  17. M. Iida and T. Sueyoshi, “A shape evaluation of circuit area for reconfigurable logic device,” in Proceedings of International Technical Conference On Circuits/System, Computers and Communications (ITC-CSCC '03), vol. 3, pp. 1595–1598, Kang-Won, Korea, July 2003.
  18. T. Higuchi, M. Iwata, D. Keymeule et al., “Development of adaptive device,” in Proceedings of IEICE General Conference, vol. A-3-14, p. 100, Kyoto, Japan, March 1998.
  19. P. Jamieson and J. Rose, “Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters,” in Proceedings of IEEE International Conference on Field Programmable Technology (FPT '06), pp. 1–8, Bangkok, Thailand, December 2006. View at Publisher · View at Google Scholar
  20. T. Sueyoshi and M. Iida, “Configurable and reconfigurable computing for digital signal processing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 3, pp. 591–599, 2002. View at Google Scholar
  21. Xilinx, Inc., Xilinx Virtex-4 Data Sheet, 2006.
  22. Opencores org, http://www.opencores.org.
  23. J. Cong and Y. Ding, “Flowmap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 1, pp. 1–12, 1994. View at Publisher · View at Google Scholar
  24. J. Cong and S. Xu, “Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '98), pp. 40–45, San Jose, Calif, USA, November 1998.
  25. Xilinx, Inc., Xilinx XC4000 Data Sheet, 1999.
  26. UCLA CAD-LAB, http://cadlab.cs.ucla.edu.
  27. D. Debnath and T. Sasao, “Fast Boolean matching under permutation by efficient computation of canonical form,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E87-A, no. 12, pp. 3134–3140, 2004. View at Google Scholar
  28. J. Cong and H. Huang, “Technology mapping and architecture evaluation for k/m-macrocell-based FPGAs,” ACM Transactions on Design Automation of Electronic Systems, vol. 10, no. 1, pp. 3–23, 2005. View at Google Scholar
  29. Y. Hu, S. Das, S. Trimberger, and L. He, “Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '07), pp. 188–193, San Jose, Calif, USA, November 2007. View at Publisher · View at Google Scholar
  30. K. McElvain, “IWLS'93 benchmark set: version 4.0,” in Proceedings of MCNC International Workshop on Logic Synthesis (IWLS '93), Tahoe City, Calif, USA, May 1993.
  31. K. Mizumoto, T. Tanizaki, S. Kobayashi et al., “A multi matrix-processor core architecture for real-time image processing SoC,” in Proceedings of IEEE Asian Solid-State Circuits Conference (ASSCC '07), pp. 180–183, Fukuoka, Japan, November 2007. View at Publisher · View at Google Scholar
  32. M. J. Myjak and J. G. Delgado-Frias, “A medium-grain reconfigurable architecture for DSP: VLSI design, benchmark mapping, and performance,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 1, pp. 14–23, 2008. View at Publisher · View at Google Scholar
  33. I. Kuon and J. Rose, “Measuring the gap between FPGAs and ASICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, pp. 203–215, 2007. View at Publisher · View at Google Scholar
  34. W. M. Fang and J. Rose, “Modeling routing demand for early-stage FPGA architecture development,” in Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays (FPGA '08), pp. 139–148, Monterey, Calif, USA, February 2008. View at Publisher · View at Google Scholar