An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Table 2

Output logic pattern of the BLE (CP = 0).

	Four-input variable		Three-input variable
AS	𝑑𝑡	𝑑𝑠	𝑑𝑡	𝑑𝑠
0	182/65,536	24/65,536	120/256	43/256
1	230/65,536	24/65,536	148/256	43/256
Total	446/65,536 (0.68%)		206/256 (80.47%)