An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Table 4

Number of logic cells and mapping delay.

Circuit	No. of logic cells		Mapping delay [ns]
	(A)	(B)	(A)	(B)
C7552	563	410	19.9	15.4
s5378	430	262	14.9	12.7
C2670	158	96	17.3	12.7
misex3	1,855	1,667	17.7	17.5
seq	1,452	1,006	17.5	17.4
ac97	4,154	2,145	10.1	7.7
aes	11,590	4,633	20.5	19.9
biquad	791	578	25.1	20.2
sha256	3,499	1,719	17.7	14.9
vga	780	385	12.8	12.7