Research Article
An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
Table 5
Normalized
delay, area, and configuration data.
| | Circuit | Mapping delay | Area | Data | | (A) | (B) | (A) | (B) | (A) | (B) |
| | C7552 | 1.00 | 0.77 | 1.00 | 0.73 | 1.00 | 0.73 | | s5378 | 1.00 | 0.85 | 1.00 | 0.61 | 1.00 | 0.61 | | C2670 | 1.00 | 0.73 | 1.00 | 0.61 | 1.00 | 0.61 | | misex3 | 1.00 | 0.99 | 1.00 | 0.90 | 1.00 | 0.90 | | seq | 1.00 | 0.99 | 1.00 | 0.69 | 1.00 | 0.69 |
| | ac97 | 1.00 | 0.76 | 1.00 | 0.52 | 1.00 | 0.52 | | aes | 1.00 | 0.97 | 1.00 | 0.40 | 1.00 | 0.40 | | biquad | 1.00 | 0.80 | 1.00 | 0.73 | 1.00 | 0.73 | | sha256 | 1.00 | 0.84 | 1.00 | 0.49 | 1.00 | 0.49 | | vga | 1.00 | 0.99 | 1.00 | 0.49 | 1.00 | 0.49 |
| | Ave. | 1.00 | 0.87 | 1.00 | 0.62 | 1.00 | 0.62 |
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