An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Table 6

Logic depth, area, and data for different architectures.

Circuit	VGLC			Virtex-4
	Depth	Area	Data	Depth	Area	Data
C7552	6	273,060	11,070	8	167,480	13,825
s5378	5	174,492	7,074	6	132,288	10,920
C2670	5	63,936	2,592	7	45,156	3,728
misex3	7	1,110,222	45,009	7	592,328	48,895
seq	7	669,996	27,162	7	506,680	41,825
ac97	3	1,428,570	57,915	4	1,225,996	101,203
aes	8	3,085,578	125,091	8	1,982,624	163,660
biquad	18	384,948	15,606	25	274,328	22,645
sha256	48	1,144,854	46,413	88	1,098,372	90,668
vga	11	256,410	10,395	18	272,632	22,505
circuit	4-LUT			6-LUT
	Depth	Area	Data	Depth	Area	Data
C7552	8	154,840	12,640	6	316,892	30,418
s5378	6	124,852	10,192	5	291,066	27,939
C2670	7	41,748	3,408	5	76,082	7,303
misex3	7	547,624	44,704	7	1,022,570	98,155
seq	7	468,440	38,240	6	1,173,338	112,627
ac97	4	1,115,828	91,088	4	1,885,298	180,967
aes	8	1,833,776	149,696	7	4,150,308	398,382
biquad	26	255,192	20,832	22	442,532	42,478
sha256	168	1,015,476	82,896	168	2,228,016	213,864
vga	33	250,880	20,480	33	517,916	49,714