An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Table 7

Normalized logic depth, area, and configuration data.

Circuit	Virtex-4			4-LUT			6-LUT
	Depth	Area	Data	Depth	Area	Data	Depth	Area	Data
C7552	1.33	0.61	1.25	1.33	0.57	1.14	1.00	1.16	2.75
s5378	1.20	0.76	1.54	1.20	0.72	1.44	1.00	1.67	3.95
C2670	1.40	0.71	1.44	1.40	0.65	1.31	1.00	1.19	2.82
misex3	1.00	0.53	1.09	1.00	0.49	0.99	1.00	0.92	2.18
seq	1.00	0.76	1.54	1.00	0.70	1.41	0.86	1.75	4.15
ac97	1.33	0.86	1.75	1.33	0.78	1.57	1.33	1.32	3.12
aes	1.00	0.64	1.31	1.00	0.59	1.20	0.88	1.35	3.18
biquad	1.39	0.71	1.45	1.44	0.66	1.33	1.22	1.15	2.72
sha256	1.83	0.96	1.95	3.50	0.89	1.79	3.50	1.95	4.61
vga	1.64	1.06	2.16	3.00	0.98	1.97	3.00	2.02	4.78
Min.	1.00	0.53	1.09	1.00	0.49	0.99	0.86	0.92	2.18
Max.	1.83	1.06	2.16	3.50	0.98	1.97	3.50	2.02	4.78
Ave.	1.31	0.76	1.55	1.62	0.70	1.42	1.48	1.45	3.43