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International Journal of Reconfigurable Computing
Volume 2008, Article ID 674340, 14 pages
http://dx.doi.org/10.1155/2008/674340
Research Article

Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation

1Kellogg College, University of Oxford, 62 Banbury Road, Oxford OX2 6PN, UK
2Oxford University Computing Laboratory, Wolfson Building, Parks Road, Oxford OX1 3QD, UK
3Celoxica Ltd., 66 Milton Park, Abingdon, Oxfordshire OX14 4RX, UK

Received 21 June 2008; Accepted 18 August 2008

Academic Editor: Gustavo Sutter

Copyright © 2008 Johan Ditmar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs.