The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="736203.fig.006a" src="https://static.hindawi.com/articles/ijrc/volume-2008/736203/figures/736203.fig.006a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Type 1: Column based small EBs near large EBs</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="736203.fig.006b" src="https://static.hindawi.com/articles/ijrc/volume-2008/736203/figures/736203.fig.006b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Type 2: Group of large EBs is surrounded by small EBs and CLBs</td></tr></table></td></tr><tr class="fig-image" id="c"><td><img alt="736203.fig.006c" src="https://static.hindawi.com/articles/ijrc/volume-2008/736203/figures/736203.fig.006c.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(c) </b>Type 3: Each large EB is surrounded by small EBs and CLBs</td></tr></table></td></tr></table>

<table>Various positions of the multiple EBs.</table>

International Journal of Reconfigurable Computing

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Figure 6

Figure 6: The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units 