Research Article
Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology
Table 2
Qualitative comparison between TPR and our proposed solution.
| | Feature | TPR [2] | PR3D [3] | 3DPRO (Proposed) |
| | Architecture exploration | Yes | No | Yes | | Measure delay | Yes | Yes | Yes | | Measure wirelength | Yes | Yes | Yes | | Measure power | No | Yes | Yes | | Supported switch boxes | Subset Wilton Universal | ASIC devices | Designer specified | | Heterogeneous interconnect (simultaneously 2D/3D SBs) | No | Yes | Yes | | Vias exploration | No | No | Yes | | Part of complete framework | No | No | Yes |
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