Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="145130.fig.011a" src="https://static.hindawi.com/articles/ijrc/volume-2009/145130/figures/145130.fig.011a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Delay-ALUT product</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="145130.fig.011b" src="https://static.hindawi.com/articles/ijrc/volume-2009/145130/figures/145130.fig.011b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Delay-DSP element product</td></tr></table></td></tr></table>

<table>The Delay-ALUT product and the Delay-DSP element
product.</table>

International Journal of Reconfigurable Computing

fig11

Figure 11

Figure 11: Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs 