Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

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<tspan style="font-size: 12.50px; " x="6.2515001" y="0">8</tspan>
<tspan style="font-size: 12.50px; " x="15.278666" y="0">×</tspan>
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</svg>-bit multiplication using 18 × 18-bit embedded blocks.</table>

International Journal of Reconfigurable Computing

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Figure 5

Figure 5: Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs 