Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

Table 1

Decomposition of input bit sizes for large size multipliers.

Segments	Range 1: double decomposition	Range 2: single decomposition
	{2≤𝜆1≤[𝑡−(𝑚−1)]}+(𝑚−1)×(𝑛−1)	{[(𝑡+1)−(𝑚−1)]≤𝜆1≤𝑛}+(𝑚−1)×(𝑛−1)
m = 2	37 to 52	53 to 71
m = 3	72 to 86	87 to 106
m = 4	107 to 120	121 to 141
m = 5	142 to 154	155 to 176
m = 6	177 to 188	189 to 211
m = 7	212 to 222	223 to 246
m = 8	247 to 256	257 to 281