Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

Table 2

The ranges of input bit size with special cases for decompositions.

Range/segments	Range 1	Special cases of Range 1	Range 2	Special cases of Range 2
	[40+35×(𝑚−2)] to [18+34×(𝑚−1)]	[19+34×(𝑚−1)] to [21+34×(𝑚−1)]	[22+34×(𝑚−1)] to [36+35×(𝑚−1)]	[37+35×(𝑚−1)] to [39+35×(𝑚−1)]
m = 2	40 to 52	53 to 55	56 to71	72 to 74
m = 3	75 to 86	87 to 89	90 to 106	107 to 109
m = 4	110 to 120	121 to 123	124 to 141	142 to 144
m = 5	145 to 154	155 to 157	158 to 176	177 to 179
m = 6	180 to 188	189 to 191	192 to 211	212 to 214
m = 7	215 to 222	223 to 225	226 to 246	247 to 249
m = 8	250 to 256	257 to 259	260 to 281	282 to 284