Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

Table 3

Result of a 256×256-bit multigranular signed multiplier.

	Delay (ns)	Number of ALUTs	Number of DSP elements	Delay-ALUT product	Delay-DSP-element product
Standard	41.530	16050	449	666557	18647
Multigranular	32.487	4577	450	148693	14619
Saving (%)	21.775	71.483	−0.223	77.692	21.600