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International Journal of Reconfigurable Computing
Volume 2009, Article ID 162416, 12 pages
http://dx.doi.org/10.1155/2009/162416
Research Article

Multilevel Simulation of Heterogeneous Reconfigurable Platforms

1Université Européenne de Bretagne, 35000 Rennes, France
2CNRS, UMR 3192 Lab-STICC, ISSTB, Université de Brest, 20 avenue Le Gorgeu, 29285 Brest, France

Received 17 December 2008; Accepted 15 April 2009

Academic Editor: Gilles Sassatelli

Copyright © 2009 Damien Picard and Loic Lagadec. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper presents a general system-level simulation and testing methodology for reconfigurable System-on-Chips, starting from behavioral specifications of system activities to multilevel simulations of accelerated tasks running on the reconfigurable circuit. The system is based on a common objectoriented environment that offers valuable debugging and probing facilities as well as integrated testing features. Our system brings these benefits to the hardware simulation, while enforcing validation through characterization tests and interoperability through on-demand mainstream tools connections. This framework has been partially developed in the scope of the EU Morpheus project and is used to validate our contribution to the spatial design task.