vMAGIC—Automatic Code Generation for VHDL

Algorithm 2

VHDL output of the example Java program. The indentation and the notation of keywords is governed by the String Template file and can be changed to fit the developers needs.

1  ENTITY   test   IS

2      PORT (

3           din : IN STD_LOGIC_VECTOR(7 DOWNTO  0);

4           dout :  OUT STD_LOGIC_VECTOR(7 DOWNTO  0);

5           LRESET_N : IN  std_logic ;

6           clk : IN   std_logic

7           );

8  END;

9

10  ARCHITECTURE  beh  OF  test IS

11    COMPONENT  test IS

12              PORT (

13                    din : IN STD_LOGIC_VECTOR(7 DOWNTO  0);

14                    dout :  OUT  STD_LOGIC_VECTOR(7 DOWNTO  0)

15                );

16      END COMPONENT;

17      SIGNAL  din_int : STD_LOGIC_VECTOR(7 DOWNTO  0);

18      SIGNAL  dout_int : STD_LOGIC_VECTOR(7 DOWNTO  0);

19  BEGIN

20     inst :  test

21         PORT MAP (

22                    din => din_int,

23                    dout => dout_int

24                    );

25     regp_din : PROCESS  (clk, LRESET_N)

26    BEGIN

27           IF  LRESET_N = '0' THEN

28                 din_int <= "00000000";

29           ELSIF  clk ' event AND  clk = '1' THEN

30                 din_int <= din ;

31           END IF;

32      END PROCESS;

33      regp_dout : PROCESS (clk, LRESET_N)

34      BEGIN

35            IF  LRESET_N = '0' THEN

36                  dout2 <= "00000000";

37            ELSIF  clk'event AND  clk = '1' THEN

38                 dout <= dout_int;

39            END IF;

40      END PROCESS;

41 END;