Table of Contents Author Guidelines Submit a Manuscript
International Journal of Reconfigurable Computing
Volume 2009 (2009), Article ID 219140, 9 pages
Research Article

Pipeline FFT Architectures Optimized for FPGAs

1Department of Electronic Engineering, Tsinghua University, Beijing 100084, China
2Department of Electrical and Computer Engineering, George Mason University, 4400 University Drive, Fairfax, VA 22030, USA

Received 28 February 2009; Accepted 23 June 2009

Academic Editor: Cesar Torres

Copyright © 2009 Bin Zhou et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. L. R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing, Prentice-Hall, Upper Saddle River, NJ, USA, 1975.
  2. E. H. Wold and A. M. Despain, “Pipeline and parallel-pipeline FFT processors for VLSI implementation,” IEEE Transactions on Computers, vol. 33, no. 5, pp. 414–426, 1984. View at Google Scholar
  3. G. Bi and E. V. Jones, “A pipelined FFT processor for word-sequential data,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 37, no. 12, pp. 1982–1985, 1989. View at Publisher · View at Google Scholar
  4. S. He and M. Torkelson, “A new approach to pipeline FFT processor,” in Proceedings of the 10th International Parallel Processing Symposium (IPPS '96), pp. 766–770, Honolulu, Hawaii, USA, April 1996.
  5. J.-Y. Oh and M.-S. Lim, “New radix-2 to the 4th power pipeline FFT processor,” IEICE Transactions on Electronics, vol. E88-C, no. 8, pp. 1740–1746, 2005. View at Publisher · View at Google Scholar
  6. T. Sansaloni, A. Pérez-Pascual, V. Torres, and J. Valls, “Efficient pipeline FFT processors for WLAN MIMO-OFDM systems,” Electronics Letters, vol. 41, no. 19, pp. 1043–1044, 2005. View at Publisher · View at Google Scholar
  7. S. Johansson, S. He, and P. Nilsson, “Wordlength optimization of a pipelined FFT processor,” in Proceedings of the 42nd Midwest Symposium on Circuits and Systems, vol. 1, pp. 501–503, 1999.
  8. S. Sukhsawas and K. Benkrid, “A high-level implementation of a high performance pipeline FFT on Virtex-E FPGAs,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI '04), pp. 229–232, February 2004.
  9. Xilinx, Inc., “High-Performance 1024-Point Complex FFT/IFFT V2.0,” San Jose, Calif, USA, July 2000,
  10. Sundance Multiprocessor Technology Ltd., 1024-Point Fixed Point FFT Processor, July 2008,
  11. P. Kabal and B. Sayar, “Performance of fixed-point FFT's: rounding and scaling considerations,” in Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '86), pp. 221–224, 1986.
  12. B. Zhou and D. Hwang, “Implementations and optimizations of pipeline FFTs on Xilinx FPGAs,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig '08), pp. 325–330, 2008. View at Publisher · View at Google Scholar
  13. Xilinx, Inc., “Xilinx Fast Fourier Transform V3.2 Product Specification,” San Jose, Calif, USA, January 2006.