Pipeline FFT Architectures Optimized for FPGAs

Table 1

Hardware resource requirements comparison of pipeline FFT architectures (based on [4]).

	Complex multipliers	Complex adders	Memory size	Control logic	Comp. Utilization
					add/sub	Multiplier
R2SDF	log2𝑁−2	2log2𝑁	𝑁−1	simple	50%	50%
R4SDF	log4𝑁−1	8log4𝑁	𝑁−1	medium	25%	75%
R4SDC	log4𝑁−1	3log4𝑁	2𝑁−2	complex	100%	75%
R2^2SDF	log4𝑁−1	4log4𝑁	𝑁−1	simple	75%	75%
R2MDC	log2𝑁−2	2log2𝑁	3𝑁/2−2	simple	50%	50%
R4MDC	3(log4𝑁−1)	8log4𝑁	5𝑁/2−4	medium	25%	25%