Research Article
Pipeline FFT Architectures Optimized for FPGAs
Table 6
Performance comparison versus prior art on Virtex-E devices.
| FFT Design | Point | Input data | Twiddle factor | Slices | Block | Max. speed | Latency | Transform time | Throughput | Throughput/area | size | width | width | RAM | (MH) | (Cycle) | Cycles | Time (s) | (MS/s) | (MS/s/slice) |
| Amphion [8] | 1024 | 13 | 13 | 1639 | 9 | 57 | 5097 | 4096 | 71.86 | 14.25 | 0.009 | Xilinx [8, 9] | 1024 | 16 | 16 | 1968 | 24 | 83 | 4096 | 4096 | 49.35 | 20.75 | 0.011 | Sundance [10] | 1024 | 16 | 10 | 8031 | 20 | 49 | 1320 | 1320 | 27.00 | 49.00 | 0.006 | Suksawas R22SDF [8] | 1024 | 16 | 16 | 7365 | 28 | 82 | 1099 | 1024 | 12.49 | 82.00 | 0.011 | Our R22SDF | 1024 | 16 | 16 | 5008 | 32 | 95.0 | 1042 | 1024 | 10.78 | 95.00 | 0.019 | Our R4SDC | 1024 | 16 | 16 | 7052 | 32 | 94.2 | 1041 | 1024 | 10.87 | 94.20 | 0.013 |
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