International Journal of Reconfigurable Computing / 2009 / Article / Tab 6

Research Article

Pipeline FFT Architectures Optimized for FPGAs

Table 6

Performance comparison versus prior art on Virtex-E devices.

FFT DesignPointInput dataTwiddle factorSlicesBlockMax. speedLatencyTransform timeThroughputThroughput/area
sizewidthwidthRAM(MH)(Cycle)CyclesTime ( s)(MS/s)(MS/s/slice)

Amphion [8]1024131316399575097409671.8614.250.009
Xilinx [8, 9]10241616196824834096409649.3520.750.011
Sundance [10]10241610803120491320132027.0049.000.006
Suksawas R22SDF [8]10241616736528821099102412.4982.000.011
Our R22SDF1024161650083295.01042102410.7895.000.019
Our R4SDC1024161670523294.21041102410.8794.200.013

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