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International Journal of Reconfigurable Computing
Volume 2009, Article ID 259837, 13 pages
Research Article

FPGA Interconnect Topologies Exploration

LIP6, Université Pierre et Marie Curie, 4, Place Jussieu, 75252 Paris, France

Received 1 December 2008; Accepted 20 July 2009

Academic Editor: J. Manuel Moreno

Copyright © 2009 Zied Marrakchi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR-style Mesh.