International Journal of Reconfigurable Computing / 2009 / Article / Fig 12

Research Article

Software Toolchain for Large-Scale RE-NFA Construction on FPGA

Figure 12

Clock frequency and LUT usage of group of 64-state synthetic REMEs versus number of REMEs implemented. Solid lines (left scale) are clock frequencies; dashed lines (right scale) are number of LUTs.
301512.fig.0012

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