Software Toolchain for Large-Scale RE-NFA Construction on FPGA

<table>REM circuits constructed by mapping Figure <a href="../fig5/">5</a> directly to HDL. The <svg height="9.4750004" id="M154" style="vertical-align:-0.273pt" version="1.1" viewbox="0 0 10.1 9.4750004" width="10.1" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,9.075)"><path d="M573 255q0 -114 -81.5 -194.5t-197.5 -80.5t-197.5 80.5t-81.5 194.5t81.5 194.5t197.5 80.5t197.5 -80.5t81.5 -194.5zM520 280q-9 80 -64.5 137t-132.5 67v-204h197zM265 280v204q-77 -10 -132.5 -67t-64.5 -137h197zM265 26v204h-197q9 -80 64.5 -137t132.5 -67z
M520 230h-197v-204q77 10 132.5 67t64.5 137z" id="x2295"></path></g>
</svg> symbols represent logic <span style="font-family:monospace">OR</span> gates.</table>

International Journal of Reconfigurable Computing

fig6

Figure 6

Figure 6: Software Toolchain for Large-Scale RE-NFA Construction on FPGA 