Speeding Up FPGA Placement via Partitioning and Multithreading

Table 2

Qualitative comparison of the proposed parallel VPR placement algorithm against previously proposed parallel placement algorithms from the FPGA domain. NA stands for not available.

	Type of	Speedup	Number	Solution	No.	Parallelization	Amount
	algorithm	[×]	of cores/	degradation	test cases	approach	of code	Domain	Availability
			machines	[%]	tested		change
This work	Region-based SA	2.5×	4	WL: 2.36%	31	Multithreading	Medium	FPGA	Public
				Delay: 3.2%
Ludwin et al. [14]	Move accel. SA	2.2×	4	WL: 0.0%	8	Multithreading	Large	FPGA	Commercial ‘08
Haldar et al. [16]	Region-based SA	1–1.5×	2–6	WL: 7%–18%	5	Distributed	Medium	FPGA	NA ‘00
Haldar et al. [16]	Markov chain SA	1.2–4.0×	2–6	WL: 7%–40%	5	Distributed	Large	FPGA	NA ‘00
Chan and Schlag [18]	Analytical	2×	3	Delay: 1%	10	Distributed	Large	FPGA	NA ‘07