Research Article
A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications
Table 2
Throughput and complex multiplier requirements for reconfigurable DFT implementations.
| Architecture | Number of complex Multipliers | Throughput: Clk. Cycles per point DFT | Constraints on |
| 2D Systolic [24] | | | | Base-4 [21] | | | | Modular [19] | | | | CSoC [29] | | | | RADComm [28] | | | | RSA [Proposed] | | | | | | | | | |
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