A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications

Table 2

Throughput and complex multiplier requirements for reconfigurable DFT implementations.

Architecture	Number of complex Multipliers	Throughput: Clk. Cycles per 𝑁 point DFT	Constraints on 𝑁
2D Systolic [24]	𝑁	𝑁3+𝑁4+1	𝑁=𝑁3∗𝑁4(𝑁3∗𝑁4=2^𝑛)
Base-4 [21]	𝑁34	𝑁4+𝑁^244+4𝑁4+28	𝑁=𝑁3∗𝑁4(𝑁3∗𝑁4=256𝑛)
Modular [19]	𝑁2	𝑁	𝑁=2^𝑛
CSoC [29]	4	𝑁2(8)log2^𝑛	𝑁=2^𝑛
RADComm [28]	𝑁	𝑁	𝑁
RSA [Proposed]	𝑁4	𝑁4	𝑁=4𝑛
	(𝑁+2)4	𝑁2	𝑁=4𝑛+2
	(𝑁−1)2	(𝑁−1)2	𝑁=2𝑛+1