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International Journal of Reconfigurable Computing
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International Journal of Reconfigurable Computing
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2009
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Article
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Tab 5
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Research Article
A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications
Table 5
Throughput and hardware requirement for the 2-channel, 8-tap Polyphase filter.
Polyphase filter
Logic resources
Throughput (Gbps)
Slice FF
7797 (3.8%)
4-Input LUT
31194 (15.3%)
2.64