An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="631490.fig.0011a" src="https://static.hindawi.com/articles/ijrc/volume-2009/631490/figures/631490.fig.0011a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Feistel decryption network</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="631490.fig.0011b" src="https://static.hindawi.com/articles/ijrc/volume-2009/631490/figures/631490.fig.0011b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Feistel encryption network</td></tr></table></td></tr></table>

<table>TDES encryption and decryption schemes (Feistel network).</table>

International Journal of Reconfigurable Computing

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Figure 11

Figure 11: An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography 

Figure 11 | An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography 