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International Journal of Reconfigurable Computing
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International Journal of Reconfigurable Computing
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2009
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Article
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Tab 4
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Research Article
An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography
Table 4
HLS-based TDES IP versus optimized IPs.
Helicon
Xilinx
HLS (RAM)
HLS (LUT)
Slices
467
16181
2877
4183
Max frequency (MHz)
196
207
170
162
Throughput at 100 MHz
255.6 Mbps
6.43 Gbps
305 Mbps
305 Mbps