Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="703267.fig.002a" src="https://static.hindawi.com/articles/ijrc/volume-2009/703267/figures/703267.fig.002a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Arbitrary</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="703267.fig.002b" src="https://static.hindawi.com/articles/ijrc/volume-2009/703267/figures/703267.fig.002b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>LSB</td></tr></table></td></tr><tr class="fig-image" id="c"><td><img alt="703267.fig.002c" src="https://static.hindawi.com/articles/ijrc/volume-2009/703267/figures/703267.fig.002c.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(c) </b>MSB</td></tr></table></td></tr></table>

International Journal of Reconfigurable Computing

fig2

Figure 2

Figure 2: Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs 