Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs

Figure 5

UWL versus MWL: homogeneous implementations (II).

(a) IIR₄, 𝜎²=10⁻³

(b) IIR₄, 𝜎²=10⁻³, 𝜆=17

(c) FIR₈, 𝜎²=10⁻⁴

(d) FIR₈, 𝜎²=10⁻⁴, 𝜆=8