Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs

Table 2

UWL versus MWL wordlength optimization.

Signal	𝜎^2=10^−5		𝜎^2=10^−6
	UWL	MWL	UWL	MWL
	(𝑝,𝑛)	(𝑝,𝑛)	(𝑝,𝑛)	(𝑝,𝑛)
𝑎	(1,9)	(−1,8)	(1,11)	(−1,10)
𝑏	(1,9)	(−1,2)	(1,11)	(−1,5)
𝑐	(1,9)	(−1,7)	(1,11)	(−1,8)
𝑚1	(1,9)	(1,9)	(1,11)	(1,10)
𝑚2	(1,9)	(−5,3)	(1,11)	(−5,4)
𝑠1	(1,9)	(1,9)	(1,11)	(1,10)
𝑠2	(1,9)	(1,8)	(1,11)	(1,10)
𝑑	(1,9)	(1,8)	(1,11)	(1,10)