Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs

Table 3

UWL versus MWL for homogeneous architectures.

Bench.	𝜎^2	Area improvement (%)
		Min	Max	Mean
ITU	10^−1	51.36	77.66	68.32
	10^−2	48.44	76.31	66.41
	10^−3	46.51	75.40	65.13
LAT3	10^−3	44.07	44.07	44.07
	10^−4	33.66	33.66	33.66
	10^−5	33.62	49.89	45.42
IIR4	10^−3	37.85	49.86	39.69
	10^−4	34.30	63.55	50.65
	10^−5	37.08	64.99	52.72
FIR8	10^−3	40.28	47.68	43.54
	10^−4	24.16	28.10	25.14
	10^−5	22.04	25.73	22.82
All		22.04	77.66	46.46