International Journal of Reconfigurable Computing / 2009 / Article / Fig 10

Research Article

Analysis and Design of a Context Adaptable SAD/MSE Architecture

Figure 10

(a) Systolic array architecture for block computation ( ). Current pixels are stored in-place and reference pixels from blocks ( , etc.) are fed into the array. D represents a single clock cycle delay. (b) Design of “light” PE. It is shown as two modules: and .

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