International Journal of Reconfigurable Computing / 2009 / Article / Tab 6

Research Article

Analysis and Design of a Context Adaptable SAD/MSE Architecture

Table 6

Evaluation of proposed architecture against all related motion estimation architectures (time taken represents number of clock cycles for computing 16 4 4 SADs).

Time taken (clocks) Latency (clocks) Memory bandwidth (bits/clock) Local (bits) Global (bits) Fanout (out/in) LUT FF

Ou et al. [5] 256 8 2048 352 32 16 12544 8192
Chen et al. (Type I) [6] 272 16 256 1920 0 4 3584 768
Chen et al. (Type II) [6] 272 17 128 6144 0 0 3968 2048
Tuang, Chang, Jen [7] 256 256 16 3840 256 0 53240 4096
Vos, Stegherr [3] 289 32 24 1792 256 2 53368 14592
Roma, Sousa [8] 289 32 24 1792 256 2 53368 13568
Komarek, Pirsch (AB1) [4] 8192 31 256 288 0 2 136 152
Komarek, Pirsch (AB2) [4] 512 32 256 4224 0 2 2176 2320
Komarek, Pirsch (AS1) [4] 8192 33 16 768 0 2 256 640
Komarek, Pirsch (AS2) [4] 256 33 4096 9792 0 2 3232 6280
Yeo, Hu [9] 289 256 24 4096 120 2 4224 4096
Yang, Sun, Wu (Type I) [2] 4096 256 24 512 0 16 384 640
Yang, Sun, Wu (Type II) [2] 4096 256 24 640 0 16 256 768
Lai, Chen [10] 256 256 24 8192 0 256 36864 6144
Kittitornkun, Hu [11] 289 289 32 4096 120 2 4096 8192
Proposed 271 7 128 7144 0 16 67584 36864

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