Selected Papers from ReCoSoc 2008View this Special Issue
Editorial | Open Access
Selected Papers from ReCoSoC 2008
The fourth edition of the Reconfigurable Communication-centric Systems-on-Chip workshop (ReCoSoC 2008) was held in Barcelona, Spain, from July 9 to 11, 2010.
ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state-of-the-art research around SoC-related topics through plenary invited papers and posters. In this event the years before, ReCoSoC had several keynotes given by internationally renowned speakers as well as special events like tutorials. ReCoSoC is a 3-day long event which endeavours to encourage scientific exchanges and collaborations. ReCoSoC aims to provide a prospective view of tomorrow's challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability.
This special issue covers actual and future trends on reconfigurable computing given by academic and industrial specialists from all over the world. The papers presented in this special issue were selected from all ReCoSoC 2008 submissions and were peer reviewed for the final publication in this journal.
The topics of the special issue cover all levels of abstraction in the field of applications, tools, and design methodology. The paper by Imran Quadri et al. “High level modelling of dynamic and reconfigurable FPGAs’’ shows one approach to hide the complexity of the novel paradigm of reconfigurable computing from the developer. Also “vMAGIC—automatic code generation for VHDL’’ by Christopher Pohl et al. Underlines the fact that novel design tools are urgently required to handle the huge design space provided by reconfigurable hardware architectures. Additionally to this, the papers by Thilo Piontek, Diana Göhringer, Damien Picard, and Kurt Franz Ackermann contribute to the very important research topic of novel tools, new design methodologies, and new paradigms. A new taxonomy is introduced by Göhringer and the coauthors with the paper “A taxonomy of reconfigurable single-/multiprocessor systems-on-chip.’’ It shows the complexity of the new degrees of freedom in terms of run-time adaptivity and presents a solution to classify the different approaches provided by academics and industry.
The novel trends in self organizing and bioinspired hardware are described in the paper by Jim Harkin et al. where a reconfigurable and biologically inspired paradigm for computation is presented. Christophe Bobda and the coauthors show the exploitation of self organization in networked systems in his paper.
All techniques for reconfigurable hardware need to be implemented on real physical hardware. The papers which present low-level methods for reconfigurable hardware by Christian Schuck, Stephane Chevobbe, Zied Marrakchi, and their coauthors describe techniques and methods which are used to manipulate reconfigurable hardware on signal level while design and run-time.
Last but not least, system-on-chip architectures and algorithms and certainly multiprocessor systems became a very important topic. Topics like efficient task mapping and message passing are described in the paper by Peter Zipf et al. and also in the paper by Gabriel Marchesan. The paper “A system on a programmable chip architecture for data-dependent superimposed training channel estimation” by Fernando Martín del Campo describes a novel approach for channel estimation in wireless communication systems using reconfigurable hardware.
J. Manuel Moreno
Copyright © 2009 Michael Hübner et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.