A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation

Table 1

Computational complexity of the stages of the DDST channel estimation algorithm.

Stage	Complexity
Input buffer	𝑂(1)
DC offset	𝑂(𝑛^2)
Carry frequency offset	𝑂(𝑛)
Training sequence synchronization	𝑂(𝑛^2)
Block synchronization	𝑂(𝑛^2)
Channel estimation	𝑂(𝑛^2)