A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors

Table 2

Core Parameters.

Parameter	Value
Processor cores	Alpha 21264
	2-issue
L1 D-Cache	32 KB
	2-way set associative, 1-cycle hit latency
	64-byte cache lines, 10 MSHRs
L1 I-Cache	64 KB
	2-way set associative, 1-cycle hit latency
	64-byte cache lines, 10 MSHRs
L2 Cache	1 MB
	8-way set associative
	5-cycle latency
	64-byte cache lines, 20 MSHRs
Shared L3 Cache	36 MB
	16-way set associative
	40-cycle latency
	64-byte cache lines, 60 MSHRs
Physical memory	512 MB
	200-cycle latency