High-Speed FPGA 10's Complement Adders-Subtractors

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="219764.fig.003a" src="https://static.hindawi.com/articles/ijrc/volume-2010/219764/figures/219764.fig.003a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Carry multiplexer</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="219764.fig.003b" src="https://static.hindawi.com/articles/ijrc/volume-2010/219764/figures/219764.fig.003b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>AND-OR circuit</td></tr></table></td></tr></table>

International Journal of Reconfigurable Computing

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Figure 3

Figure 3: High-Speed FPGA 10's Complement Adders-Subtractors 