High-Speed FPGA 10's Complement Adders-Subtractors

Table 3

Delays in ns for decimal and binary adders in Virtex-5 -2.

N (BCD digits)	Ad-I	Ad-II	M (bits)	Binary Adder
8	3.8	3.6	27	2.1
16	4.4	4.0	54	2.6
32	5.0	4.5	107	3.8
48	5.2	5.1	160	5.1
64	5.6	5.2	213	6.6
96	6.1	5.9	319	8.7