High-Speed FPGA 10's Complement Adders-Subtractors

Table 5

Area in 6-input LUTs for different adders and adders-subtractors.

Circuit	# LUTs
Adder Ad-I	8 × 𝑁
Adder Ad-II	10 × 𝑁
Binary Adder	⌈3.32×𝑁⌉
Adder-Subtractor AS-I	10 × 𝑁
Adder-Subtractor AS-II	13 × 𝑁
Binary Adder-Subtractor	⌈3.32×𝑁⌉