Reconfigurable Hardware Implementation of a Multivariate Polynomial Interpolation Algorithm

Table 4

Experimental results for subtask blocks.

	𝑑sa	Slices^∗	Slice F/F^∗	4 input LUTs^∗	FIFO16/RAMB16^∗	freq (Mhz)	𝑡𝐹 (s)	𝑡𝐶 (s)	speedup
3*Cover	64	4141 (4.65%)	4348 (2.44%)	7708 (4.33%)	9 (2.68%)	176	1.12𝐸−03	1.29𝐸−02	11.51×
	128	8279 (9.29%)	8700 (4.88%)	15054 (8.45%)	9 (2.68%)	176	5.90𝐸−04	1.29𝐸−02	21.93×
	256	16554 (18.58%)	17404 (9.77%)	30796 (17.28%)	9 (2.68%)	176	3.21𝐸−04	1.29𝐸−02	40.33×
3*P-add	64	2967 (3.33%)	3516 (1.97%)	4119 (2.31%)	7 (2.08%)	200	6.84𝐸−04	3.36𝐸−02	49.17×
	128	5885 (6.61%)	7455 (4.18%)	7156 (4.02%)	7 (2.08%)	200	3.58𝐸−04	3.36𝐸−02	93.99×
	256	11741 (13.18%)	14880 (8.35%)	14228 (7.99%)	7 (2.08%)	200	1.95𝐸−04	3.36𝐸−02	172.28×
3*Distinct	64	2680 (3.01%)	3741 (2.10%)	3173 (1.78%)	7 (2.08%)	190	7.20𝐸−04	3.37𝐸−02	46.87×
	128	5342 (6.00%)	7465 (4.19%)	6261 (3.51%)	7 (2.08%)	190	3.77𝐸−04	3.37𝐸−02	89.60×
	256	10659 (11.96%)	14903 (8.36%)	12437 (6.98%)	7 (2.08%)	190	2.05𝐸−04	3.37𝐸−02	164.25×

^∗Resource percentages are for a Virtex-4 XC4VLX200ff1513-11.