Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics

Table 1

Sequence at the beginning of the encryption.

DES Round	Initial State	0 (IP)		1
WDDL phase	Precharge (PRE)	Precharge (PRE)	Evaluation (EVA)	Precharge (PRE)	Evaluation (EVA)
LR Master	0	IP	0	LR1	0
LR Slave	0	0	IP	0	LR1