International Journal of Reconfigurable Computing

Research Article

Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics

Table 3

Statistics for Bits of R_S Register.
(a) WDDL 3DES Module without PAR Constraints
SBox 1 2 3 4
Bit of R 9 17 23 31 13 28 2 18 24 16 30 6 26 20 10 1
Timing imbalance, in ps 266 917 796 308 331 885 265 633 560 1,073 286 840 599 611 851253
Security Gain 3 1 5 1 1 6 3 1 2 11 10 6 2 4 2 1
Minimal Security Gain 1 1 2 1
SBox 5 6 7 8
Bit of R 8 14 25 3 4 29 11 19 32 12 22 7 5 27 15 21
Timing imbalance, in ps 290 686 944 1,014 1,574 261 700 666 306 340 865 262 322 1,032 348 621
Security Gain 1 2 5 7 4 2 8 1 322 2 4 1 1 3 2
Minimal Security Gain 1 1 2 1
(b) WDDL 3DES Module with Vertical Strategy
SBox 1 2 3 4
Bit of R 9 17 23 31 13 28 2 18 24 16 30 6 26 20 10 1
Timing imbalance, in ps 38 64 23 23 53 30 5 1 29 320 1 1 59 1 17
Security Gain 50 10 9 5 1 8 10 4 12 20 9 31 6 21 23 21
Minimal Security Gain 5 1 9 6
SBox 5 6 7 8
Bit of R 8 14 25 3 4 29 11 19 32 12 22 7 5 27 15 21
Timing imbalance, in ps 25 1 29 1 123 30 1 1 51 9 10 42 1 59 42
Security Gain 2 19 13— 214 5 15— 19 352 11 31 36 1 8 31
Minimal Security Gain 2 5 11 1
(c) WDDL 3DES Module with Horizontal Strategy
SBox 1 2 3 4
Bit of R 9 17 23 31 13 28 2 18 24 16 30 6 26 20 10 1
Timing imbalance, in ps 325 125 125 152 182 17614 29 156 146 65 41 38 221 42 355
Security Gain 9 8 7 2 3 10 4 1 18 15 25 11 2 5 20 5
Minimal Security Gain 2 1 15 2
SBox 5 6 7 8
Bit of R 8 14 25 3 4 29 11 19 32 12 22 7 5 27 15 21
Timing imbalance, in ps 26 39 204 136 168 139 147 247 208 166 14 150 261 50 83 182
Security Gain 2 4 2 15 110 8 11 15 23364 18 23 32 4 9 14
Minimal Security Gain 2 8 18 4