Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study

Table 2

Performance improvement of image registration and Canny edge detection on Cray XD1.

Algorithm name		Computing time (s)		Speedup	Resource utilization
		Opteron 2.4G	Cray XD1		Slices	Built-in multipliers
Image registration*	Exhaustive search	157.347	16.193	9.72	10.766 (45%)	42 (18%)
	DWT-based search^†	1.298	0.829	1.57	20.205 (85%)	108 (55%)
		End-to-end throughput (MB/s)
Canny edge detection		2.20	1.196	543.6	15.015 (63%)	200 (86%)

*The sizes of reference and test image are both 1024×1024. The search spaces of ΔΘ, Δ𝑋, and Δ𝑌 are all from −8 to +8.
^†Three levels of DWT are performed before the search, which is based on LL coefficients only.