International Journal of Reconfigurable Computing / 2010 / Article / Tab 2

Research Article

Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study

Table 2

Performance improvement of image registration and Canny edge detection on Cray XD1.

Algorithm nameComputing time (s)SpeedupResource utilization
Opteron 2.4GCray XD1SlicesBuilt-in multipliers

Image registration*Exhaustive search157.34716.1939.7210.766 (45%)42 (18%)
DWT-based search1.2980.8291.5720.205 (85%)108 (55%)
End-to-end throughput (MB/s)
Canny edge detection2.201.196543.615.015 (63%)200 (86%)

*The sizes of reference and test image are both . The search spaces of , , and are all from to .
Three levels of DWT are performed before the search, which is based on LL coefficients only.

Article of the Year Award: Outstanding research contributions of 2020, as selected by our Chief Editors. Read the winning articles.