3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans
Figure 1
(a) 2D homogeneous NoC design. A tile is composed of a router (R) and a generic processing element (PE). A PE can implement any IP/core of a given application. Routers are interconnected via physical links. (b) Custom heterogeneous NoC design.
