Research Article
Exploration of Heterogeneous FPGA Architectures
Table 3
Open core benchmarks set III.
| Circuit name | No of inputs | No of outputs | No of LUTs | No of multipliers () |
| cf_fir_3_8_8 | 42 | 22 | 214 | 4 | diffeq_f_system C | 66 | 99 | 1532 | 4 | diffeq_paj_convert | 12 | 101 | 738 | 5 | fir_scu | 10 | 27 | 1366 | 17 | iir1 | 33 | 30 | 632 | 5 | iir | 28 | 15 | 392 | 5 | rs_decoder_1 | 13 | 20 | 1553 | 13 | rs_decoder_2 | 21 | 20 | 2960 | 9 |
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