International Journal of Reconfigurable Computing / 2011 / Article / Tab 3

Research Article

Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation

Table 3

State-of-art implementations of modular multiplication architectures.

Design FPGA Clock Area Mod exp

Systolic XC5VLX110T 130 MHz 6642 Slices 3.23 ms
Multiplexed XC5VLX110T 90 MHz 5005 Slices 4.36 ms
[5] XV2VP70 101.86 MHz 5709 Slices 3.01 ms
[12] XC5VLX110T 95 MHz 3044 Slices 6 ms
[4] XC2V2000 248 MHz 4051 Slices 9.4 ms
[1] Virtex-4 150.5 MHz 2613 Slices 13.94 ms

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