Table of Contents Author Guidelines Submit a Manuscript
International Journal of Reconfigurable Computing
Volume 2011, Article ID 254730, 9 pages
Research Article

A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos

Federal University of Pelotas (UFPel), Group of Architectures and Integrated Circuits (GACI), 96010-900, Pelotas, RS, Brazil

Received 2 June 2010; Revised 21 September 2010; Accepted 27 October 2010

Academic Editor: Gustavo Sutter

Copyright © 2011 Marcel M. Corrêa et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation that targets high-definition videos. This design can process very high-definition videos like QHDTV ( 3 8 4 0 × 2 0 4 8 ) in real time (30 frames per second). It also presents an optimized arrangement of interpolated samples, which is the main key to achieve an efficient search. The interpolation process is interleaved with the SAD calculation and comparison, allowing the high throughput. The architecture was fully described in VHDL, synthesized for two different Xilinx FPGA devices, and it achieved very good results when compared to related works.